Memory devices typically include memory arrays having many memory cells, where each memory cell is configured to hold an electrical charge that represents data, such as one or more bits of data or a portion of a bit of data. Memory devices may include, for example, RAM, SRAM, DRAM, PRAM, SDRAM, and other types of memory devices. Access operations for such memory devices include write and read operations. External data is stored in the memory cells during a write operation. The stored data is retrieved from the memory cells during a read operation.
Memory arrays of memory devices are typically arranged into rows and columns of memory cells. A memory array typically includes a number of control lines, often referred to as “word lines,” each of which connects to one or more corresponding rows of memory cells. A control line may include, for example, a global word line, a local word line, or other types of control lines, as described further below. A memory array also typically includes a number of data lines, often referred to as “bit lines,” where each bit line connects to one or more corresponding columns of memory cells. In this manner, each given memory cell in a memory array is connected to at least one control line and at least one bit line. During a memory access operation, the memory device controls a voltage on a respective word line to access a memory cell on the control line, and either stores data to the memory cell or retrieves data from the memory cell using the respective bit line.
Each control line in a conventional memory array typically receives a voltage during a memory operation from a corresponding line driver. In an “active low” configuration, the voltage provided on a control line is a logic low voltage when the control line is active, and is a logic high voltage when the control line is inactive. Alternatively, in an “active high” configuration, the voltage provided on the control line is a logic high voltage when the control is active, and a logic low voltage when the control line is inactive. For example, in an active high configuration, a line driver may drive a corresponding control line to a positive voltage during a memory access operation of one of the memory cells connected to the word line. When a memory access operation is not being performed on a memory cell connected to the control line, the corresponding control line driver drives the control line to a lower positive voltage, a negative voltage, or a ground voltage, as described further below.
In some cases, control lines of a memory array may include global word lines and local word lines. For example, a memory array may be arranged as one or more memory blocks, with each memory block including a set of local word lines connected to rows of memory cells within the memory block and configured to provide a word line voltage WL to the memory cells. Each of the local word lines may be driven by a corresponding local word line driver. The local word lines found in each memory block are typically identical. For example, if a first memory block in a memory array includes a set of local word lines WL_0-WL_N, then another memory block in the memory array also typically includes a similar set of local word lines WL_0-WL_N. Thus, respective sets of local word line drivers in multiple memory blocks may be driven by a single set of global word lines GWL_0-GWL_N by selectively connecting the set of global word lines to one or more sets of local word lines. Each global word line is driven by a global word line driver that provides a line voltage, such as a global row falling (GRF) edge enable voltage, to the global word line. In some cases, the voltage provided by the global word line driver may be inverted at the local word line driver, with the inverted logic voltage being output as the local word line voltage.
A memory array operates in various modes, such as an active mode, when at least one word line in the memory array is being used to access the memory array, and an inactive mode (for example, a standby mode), when no word lines are being used to access the memory array. The memory array may enter an inactive mode, for example, when performing a static refresh operation or other operation when accessing cells of the memory array is not desirable or required.
When the memory array is in an active mode, a single word line is typically being used to access a memory cell in the memory array at any one time. When at least one of the word lines connected to the memory array is being used to access a memory cell (e.g., if any one word line is active), it is desirable to couple other word lines of the memory array (e.g., the inactive word lines) to a negative word line voltage. By connecting the inactive word lines to the negative voltage, sub-threshold leakage across the memory cells connected to these inactive word lines is reduced.
While connecting the inactive word lines to the negative voltage during an active period reduces sub-threshold leakage, it disadvantageously increases a gate induced drain leakage (GIDL) of components in the memory array. In a transistor, GIDL is generally caused by a high gate-to-drain electric field in the region of the gate that overlaps the drain. For example, an NMOS transistor may experience GIDL when a potential at its source/drain is substantially greater than a potential at its gate. Similarly, a PMOS transistor may experience GIDL when a potential at its source/drain is substantially lower than a potential at its gate.
Accordingly, when a memory array is in an inactive mode, such that no word lines are being used to access memory cells in the memory array, it is desirable to drive the word lines to a standby voltage, which may be, for example, a ground voltage or a positive voltage. To this end, a line driver may function as a voltage selection circuit configured to selectably couple a word line to either a first voltage level, such as a negative voltage level, during an active period where at least one of the word lines connected to an array are active, and to a second voltage level, such as a positive or ground voltage level, during an inactive period when each of the word lines are inactive.
FIG. 1 shows a conventional line driver 10 for a memory array, which may be used, for example, as a global word line driver. Line driver 10 includes a pull up power control circuit 12 that is configured to provide (e.g., output, generate, establish, etc.) a pull-up voltage, shown in FIG. 1 as voltage vpup. Line driver 10 also includes a pull down power control circuit 14 configured to output a pull-down voltage, shown in FIG. 1 as vpdn.
Pull-up power control circuit 12 may be configured to output a first pull-up voltage when the corresponding memory array is in an active mode and a second pull-up voltage when the corresponding array is in an inactive mode. For example, pull-up power control circuit 12 may be configured to output a first bias voltage vccp, which may be, for example, approximately 3.0 V, during an active period, and a second bias voltage vccprdec (Vccp Row Decode), which may be, for example, approximately 2.5 V, during an inactive period.
Pull-down power control circuit 14 outputs a first pull-down voltage when the corresponding memory array is in an active mode (e.g., when at least one word line driver of the memory array is performing a memory access operation), and a second pull-down voltage when the memory array is in an inactive mode (e.g., when no word line drivers of the memory array are performing a memory access operation, such as during a static refresh operation). For example, pull-down power control circuit 14 may be configured to output a negative pull-down voltage vneg, which may be, for approximately −0.3 V, during an active period, and a standby pull-down voltage, which may be, for example, approximately 1 V during an inactive period. As described further below, a negative voltage source 16 configured to provide negative pull-down voltage vneg to pull-down power control circuit 14 may also be configured to provide vneg as a gate voltage to gate voltage selection circuit 30 (described further below).
Line driver 10 includes a voltage selection circuit 20 configured to output a line driver output voltage Vout to a control line 62 (for example, a global word line or a local word line). Voltage selection circuit 20 includes a pull-up transistor 22, which may be a PMOS transistor, and a pull-down transistor 24, which may be an NMOS transistor. Pull-up transistor 22 and pull-down transistor 24 are coupled in series, with a first source/drain of pull-up transistor 22 coupled to pull-up power control circuit 12 and a second source/drain of pull-up transistor 22 coupled to a first source/drain of pull-down transistor 24 and control line 62. A second source/drain of pull-down transistor 24 is coupled to pull-down power control circuit 14. The respective gates of pull-up transistor 22 and pull-down transistor 24 share a common node that receives a gate voltage GR from a gate voltage selection circuit 30.
Gate voltage GR is controlled by gate voltage selection circuit 30 and a logic control circuit 18. Gate voltage selection circuit 30 includes first and second gate voltage selection transistors 32, 34. First gate voltage selection transistor 32 may be a PMOS transistor having a first source/drain coupled to pull up power control circuit 12 and a second source/drain coupled to a node providing gate voltage GR. Second gate voltage selection transistor 34 may be an NMOS transistor 34 having a first source/drain coupled to the node providing gate voltage GR and a second source/drain coupled to a negative voltage source 16. Negative voltage source 16 may be, for example, equal to the negative pull-down voltage vneg, and the negative voltage source 16 may be used to provide the negative pull-down voltage vneg to pull-down power control circuit 14.
During an active period of the memory array when line driver 10 is activating a word line to perform a memory access operation on a memory cell, logic control circuit 18 controls gate voltage selection circuit 30 to provide pull-up voltage vpup (e.g., vccprdec) as the gate voltage GR. During an active period of the memory array when line driver 10 is not activating a word line to perform a memory access operation on a memory cell (e.g., when at least one other word line driver of the memory array is active), logic control circuit 18 controls gate voltage selection circuit 30 to provide negative voltage vneg from negative voltage source 16 as the gate voltage GR. During an inactive period of the memory array (e.g., when no word line drivers of the memory array are active), logic control circuit 18 controls gate voltage selection circuit 30 to provide negative voltage vneg from negative voltage power source 16 as the gate voltage GR. Voltage selection circuit 20 is configured to output pull-up voltage vpup (e.g., vccprdec) to control line 62 when gate voltage GR is a negative voltage, such as vneg. Voltage selection circuit 20 is configured to output pull-down voltage vpdn (e.g., a ground or positive voltage) to control line 62 when gate voltage GR is a positive voltage, such as vpup.
Line driver 10 may be configured to act as a global word line driver for a word line of a memory array, where the output voltage Vout provided to control line 62 acts as a global word line voltage that may be inverted at a local word line driver. In this case, line driver 10 acts as a global word line driver for a memory array in an active high configuration, outputting a low logic voltage (i.e., pull-down voltage vpdn) to control line 62 as voltage Vout in order to drive a corresponding local word line driver of a word line to output a high logic value to a local word line in order to perform a memory access operation on a memory cell.
FIG. 2 illustrates voltage levels corresponding to various nodes within the conventional line driver 10 during inactive and active periods of a corresponding memory array. For example, conventional line driver 10 may be a global word line driver for a memory array having an active high configuration, where the output voltage Vout of line driver 10 acts as a global word line voltage that drives a local word line driver and is inverted at the local word line driver.
During an inactive period of the memory array, logic control circuit 18 outputs a logic high control signal to first and second gate voltage selection transistors 32, 34, such that negative pull-up voltage vneg (e.g., −0.3 V) is provided as gate voltage GR to the respective gates of pull-up transistor 22 and pull-down transistor 24. Providing vneg as gate voltage GR causes pull-up transistor 22 to conduct, providing vpup (e.g., vccprdec, which may be approximately 2.5 V) as line driver output voltage Vout at control line 62.
During an active period where line driver 10 is being used to drive a corresponding local word line driver to perform a memory access operation on a memory cell, logic control circuit 18 outputs a logic low control signal to first and second gate voltage selection transistors 32, 34, such that pull-up voltage vpup (e.g., vccp, which may be approximately 3.0 V) is provided as gate voltage GR to the respective gates of pull-up transistor 22 and pull-down transistor 24. Providing pull-up voltage vpup as gate voltage GR causes pull-down transistor 24 to conduct, providing vpdn (e.g., vneg) as line driver output voltage Vout at control line 62.
As discussed above, during an inactive period of the line driver 10 described in connection with FIGS. 1 and 2 above, the gate voltage GR of both pull-up transistor 22 and pull-down transistor 24 is equal to negative voltage vneg, which may be, for example, approximately −0.3 V. If vccprdec is, for example, approximately 2.5 V during an inactive period, this results in a voltage differential between the gate and both source/drains of pull-up transistor 22 of approximately 2.8 V. The gate and the source/drain of pull-down transistor 24 that is connected to control line 62 also includes a voltage differential of approximately 2.8 V. This voltage differential may result in undesirable GIDL during the inactive period, as well as undesirable stress on pull-up transistor 22 and/or pull-down transistor 24.
Accordingly, it is desirable to provide apparatuses and corresponding methods of operation that reduce sub-threshold leakage experienced during an active period of operation of a memory array line driver while reducing GIDL and device stress experienced during an inactive period of the line driver.